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?2003 silicon storage technology, inc. s71236-00-000 7/03 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mpf+ and combomemory are trademarks of silicon storage technology, inc. intel is a registered trademark of intel corporation. these specifications are subject to change without notice. preliminary specifications features: ? combomemories organized as: ? sst32hf1641x: 1m x16 flash + 256k x16 sram ? sst32hf3241x: 2m x16 flash + 256k x16 sram ? sst32hf3281x: 2m x16 flash + 512k x16 sram ? sst32hf6481x: 4m x16 flash + 512k x16 sram ? sst32hf64161x: 4m x16 flash + 1m x16 sram single 2.7-3.3v read and write operations concurrent operation ? read from or write to sram while erase/program flash superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention low power consumption: ? active current: 15 ma (typical) for flash or sram read ? standby current: - sst32hfx1: 60 a (typical) - sst32hfx1c: 12 a (typical) flexible erase capability ? uniform 2 kword sectors ? uniform 32 kword size blocks erase-suspend/erase-resume capabilities security-id feature ? sst: 128 bits; user: 128 bits hardware block-protection/wp# input pin ? bottom block-protection (bottom 32 kword) for sst32hf1641x/32x1x/64xx1x fast read access times: ? flash: 70 ns and 90 ns ? sram: 70 ns and 90 ns latched address and data for flash flash fast erase and word-program: ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 40 ms (typical) ? word-program time: 7 s (typical) flash automatic erase and program timing ? internal v pp generation flash end-of-write detection ? toggle bit ? data# polling cmos i/o compatibility jedec standard command set package available ? 63-ball tfbga (8mm x 10mm x 1.2mm) ? 63-ball lfbga (8mm x 10mm x 1.4mm) ? 62-ball lfbga (8mm x 10mm x 1.4mm) product description the sst32hfx1/x1c combomemory devices integrate a cmos flash memory bank with a cmos sram mem- ory bank in a multi-chip package (mcp), manufactured with sst?s proprietary, high performance superflash technology. the sst32hf1641/32x1/64xx1 devices use a pseudosram. the sst32hf1641c/32x1c/64xx1c devices use standard sram. featuring high performance word-program, the flash memory bank provides a maximum word-program time of 7 sec. to protect against inadvertent flash write, the sst32hfx1/x1c devices contain on-chip hardware and software data protection schemes. the sst32hfx1/x1c devices offer a guaranteed endurance of 10,000 cycles. data retention is rated at greater than 100 years. the sst32hfx1/x1c devices consist of two independent memory banks with respective bank enable signals. the flash and sram memory banks are superimposed in the same memory address space. both memory banks share common address lines, data lines, we# and oe#. the memory bank selection is done by memory bank enable signals. the sram bank enable signal, bes# selects the sram bank. the flash memory bank enable signal, bef# selects the flash memory bank. the we# signal has to be used with software data protection (sdp) command sequence when controlling the erase and program opera- tions in the flash memory bank. the sdp command sequence protects the data stored in the flash memory bank from accidental alteration. the sst32hfx1/x1c provide the added functionality of being able to simultaneously read from or write to the sram bank while erasing or programming in the flash memory bank. the sram memory bank can be read or written while the flash memory bank performs sector- erase, bank-erase, or word-program concurrently. all flash memory erase and program operations will automati- cally latch the input address and data signals and complete the operation in background without further input stimulus requirement. once the internally controlled erase or pro- gram cycle in the flash bank has commenced, the sram bank can be accessed for read or write. multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c sst32hf324 / 32832mb flash + 4mb sram, 32mb flash + 8mb sram (x16) mcp combomemories
2 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 the sst32hfx1/x1c devices are suited for applications that use both flash memory and sram memory to store code or data. for systems requiring low power and small form factor, the sst32hfx1/x1c devices significantly improve performance and reliability, while lowering power consumption, when compared with multiple chip solutions. the sst32hfx1/x1c inherently use less energy during erase and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to pro- gram and has a shorter erase time, the total energy con- sumed during any erase or program operation is less than alternative flash technologies. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. device operation the sst32hfx1/x1c use bes1#, bes2 and bef# to con- trol operation of either the flash or the sram memory bank. when bef# is low, the flash bank is activated for read, program or erase operation. when bes1# is low, and bes2 is high the sram is activated for read and write operation. bef# and bes1# cannot be at low level, and bes2 cannot be at high level at the same time. if all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. all address, data, and control lines are shared by flash and sram memory banks which minimizes power consump- tion and loading. the device goes into standby when bef# and bes1# bank enables are raised to v ihc (logic high) or when bef# is high and bes2 is low. concurrent read/write operation the sst32hfx1/x1c provide the unique benefit of being able to read from or write to sram, while simultaneously erasing or programming the flash. this allows data alter- ation code to be executed from sram, while altering the data in flash. see figure 26 for a flowchart. the following table lists all valid states. the device will ignore all sdp commands when an erase or program operation is in progress. note that product identification commands use sdp; therefore, these com- mands will also be ignored while an erase or program operation is in progress. flash read operation the read operation of the sst32hfx1/x1c devices is controlled by bef# and oe#. both have to be low, with we# high, for the system to obtain data from the outputs. bef# is used for flash memory bank selection. when bef# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to figure 6 for further details. c oncurrent r ead /w rite s tate t able flash sram program/erase read program/erase write
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 3 ?2003 silicon storage technology, inc. s71236-00-000 7/03 flash word-program operation the flash memory bank of the sst32hfx1/x1c devices is programmed on a word-by-word basis. before program operations, the memory must be erased first. the program operation consists of three steps. the first step is the three- byte load sequence for software data protection. the sec- ond step is to load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either bef# or we#, whichever occurs last. the data is latched on the rising edge of either bef# or we#, whichever occurs last. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or bef#, whichever occurs first. the pro- gram operation, once initiated, will be completed, within 10 s. see figures 7 and 8 for we# and bef# controlled pro- gram operation timing diagrams and figure 21 for flow- charts. during the program operation, the only valid flash read operations are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. during the command sequence, wp# should be statically held high or low. any sdp commands loaded during the internal program operation will be ignored. flash sector/block-erase operation the flash sector/block-erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. the sst32hfx1/x1c offer both sector-erase and block-erase mode. the sector architecture is based on uniform sector size of 2 kword. the block-erase mode is based on uniform block size of 32 kword. the sector- erase operation is initiated by executing a six-byte com- mand sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the address lines a ms -a 11 are used to determine the sector address. the block-erase operation is initiated by executing a six-byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the address lines a ms -a 15 are used to determine the block address. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase operation can be determined using either data# polling or toggle bit methods. see figures 12 and 13 for timing waveforms. any commands issued during the sector- or block-erase operation are ignored, wp# should be statically held high or low. erase-suspend/erase-resume commands the erase-suspend operation temporarily suspends a sector- or block-erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an erase operation. the operation is executed by issuing one byte command sequence with erase-suspend command (b0h). the device automatically enters read mode typically within 20 s after the erase-suspend command had been issued. valid data can be read from any sector or block that is not suspended from an erase operation. reading at address location within erase-suspended sectors/blocks will output dq 2 toggling and dq 6 at ?1?. while in erase-suspend mode, a word-program operation is allowed except for the sector or block selected for erase-suspend. to resume sector-erase or block-erase operation which has been suspended the system must issue erase resume command. the operation is executed by issuing one byte command sequence with erase resume command (30h) at any address in the last byte sequence. flash chip-erase operation the sst32hfx1/x1c provide a chip-erase operation, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or bef#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 5 for the command sequence, figure 10 for tim- ing diagram, and figure 25 for the flowchart. any com- mands issued during the chip-erase operation are ignored. write operation status detection the sst32hfx1/x1c provide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the soft- ware detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which ini- tiates the internal program or erase operation.
4 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either dq 7 or dq 6. in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid. ready/busy# (ry/by#) the sst32hfx1/x1c include a ready/busy# (ry/by#) output signal. during any sdp initiated operation, e.g., erase, program, id read operation, ry/by# is actively pulled low, indicating a sdp controlled operation is in progress. the status of ry/by# is valid after the rising edge of fourth we# (or bef#) pulse for program operation. for sector-, block- or bank-erase, the ry/by# is valid after the rising edge of sixth we# or (bef#) pulse. ry/by# is an open drain output that allows several devices to be tied in parallel to v dd via an external pull up resistor. ready/ busy# is in high impedance whenever oe# or bef# is high or rst# is low. there is a 1 s bus recovery time (t br ) required before valid data can be read on the data bus. new commands can be entered immediately after ry/by# goes high. flash data# polling (dq 7 ) when the sst32hfx1/x1c flash memory banks are in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the pro- gram operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immedi- ately following the completion of an internal write opera- tion, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent suc- cessive read cycles after an interval of 1 s. during inter- nal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of the fourth we# (or bef#) pulse for program opera- tion. for sector- or block-erase, the data# polling is valid after the rising edge of the sixth we# (or bef#) pulse. see figure 9 for data# polling timing diagram and figure 22 for a flowchart. toggle bits (d q6 and dq2) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. for sector-, block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or bef#) pulse. dq 6 will be set to ?1? if a read operation is attempted on an erase-suspended sector/block. if program operation is ini- tiated in a sector/block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular sector is being actively erased or erase-suspended. table 1 shows detailed status bits information. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or bef#) pulse of write operation. see figure 10 for toggle bit timing diagram and figure 22 for a flowchart. note: dq 7 and dq 2 require a valid address when reading status information. flash memory da ta protection the sst32hfx1/x1c flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. flash hardware data protection noise/glitch protection : a we# or bef# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, bef# high, or we# high will inhibit the flash write operation. this prevents inadvertent writes during power-up or power-down. table 1: w rite o peration s tatus status dq 7 dq 6 dq 2 normal operation standard program dq 7 # toggle no toggle standard erase 0 toggle toggle erase- suspend mode read from erase-suspended sector/block 1 1 toggle read from non- erase-suspended sector/block data data data program dq 7 # toggle n/a t1.0 1236
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 5 ?2003 silicon storage technology, inc. s71236-00-000 7/03 hardware bloc k protection the sst32hfx1/x1c support bottom hardware block protection, which protects the bottom 32 kword block of the device. the boot block address is 000000h-007fffh . program and erase operations are prevented on the 32 kword when wp# is low. if wp# is left floating, it is inter- nally held high via a pull-up resistor, and the boot block is unprotected, enabling program and erase operations on that block. hardware reset (rst#) the rst# pin provides a hardware method of resetting the device to read array data. when the rst# pin is held low for at least t rp, any in-progress operation will terminate and return to read mode. when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place (see figure 17). the erase or program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. flash software data protection (sdp) the sst32hfx1/x1c provide the jedec approved soft- ware data protection scheme for all flash memory bank data alteration operations, i.e., program and erase. any program operation requires the inclusion of a series of three-byte sequence. the three byte-load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte load sequence. the sst32hfx1/x1c devices are shipped with the software data protection permanently enabled. see table 5 for the specific software command codes. during sdp command sequence, invalid commands will abort the device to read mode, within t rc. the contents of dq 15 -dq 8 can be v il or v ih, but no other value, during any sdp command sequence. sram read the sram read operation of the sst32hfx1/x1c is con- trolled by oe# and bes1#, both have to be low with we# and bes2 high for the system to obtain data from the out- puts. bes1# and bes2 are used for sram bank selection. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to the read cycle timing diagram, fig- ure 3, for further details. sram write the sram write operation of the sst32hfx1/x1c is con- trolled by we# and bes1#, both have to be low, bes2 must be high for the system to write to the sram. during the word-write operation, the addresses and data are ref- erenced to the rising edge of either bes1#, we#, or the falling edge of bes2 whichever occurs first. the write time is measured from the last falling edge of bes#1 or we# or the rising edge of bes2 to the first rising edge of bes1#, or we# or the falling edge of bes2. refer to the write cycle timing diagrams, figures 4 and 5, for further details. product identification the product identification mode identifies the devices as the sst32hfxxx and manufacturer as sst. this mode may be accessed by software operations only. the hardware device id read operation, which is typically used by programmers, cannot be used on this device because of the shared lines between flash and sram in the multi-chip package. therefore, application of high voltage to pin a 9 may damage this device. users may use the software product identification operation to identify the part (i.e., using the device id) when using multi- ple manufacturers in the same socket. for details, see tables 4 and 5 for software operation, figure 14 for the software id entry and read timing diagram and figure 23 for the id entry command sequence flowchart. table 2: p roduct i dentification address data manufacturer?s id 0000h bfh device id sst32hf1641x 0001h 234bh sst32hf32x1x 0001h 235bh sst32hf64xx1x 0001h 236bh t2.0 1236
6 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 product identification mode exit/reset in order to return to the standard read mode, the software product identification mode must be exited. exiting is accomplished by issuing the exit id command sequence, which returns the device to the read operation. please note that the software reset command is ignored during an internal program or erase operation. this command may also be used to reset the device to read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g. not read correctly. see table 5 for software command codes, figure 15 for timing waveform and figure 23 for a flowchart. security id the sst32hfx1/x1c devices offer a 256-bit security id space. the secure id space is divided into two 128-bit seg- ments - one factory programmed segment and one user programmed segment. the first segment is programmed and locked at sst with a random 128-bit number. the user segment is left un-programmed for the customer to pro- gram as desired. to program the user segment of the security id, the user must use the security id word-program command. to detect end-of-write for the sec id, read the toggle bits. do not use data# polling. once this is complete, the sec id should be locked using the user sec id program lock-out. this disables any future corruption of this space. note that regardless of whether or not the sec id is locked, neither sec id segment can be erased. the secure id space can be queried by executing a three- byte command sequence with enter sec id command (88h) at address 5555h in the last byte sequence. to exit this mode, the exit sec id command should be executed. refer to table 5 for more details. design considerations sst recommends a high frequency 0.1 f ceramic capac- itor to be placed as close as possible between v dd and v ss , e.g., less than 1 cm away from the v dd pin of the device. additionally, a low frequency 4.7 f electrolytic capacitor from v dd to v ss should be placed within 1 cm of the v dd pin. i/o buffers 1236 b1.2 address buffers dq 15 - dq 8 a ms -a 0 we 1 # superflash memory sram/ psram control logic bes1# bes2 bef# oe 1 # reset# ry/by# wp# address buffers & latches lbs# ubs# dq 7 - dq 0 notes: 1. for ls and tbd? packages only: we# = wef# and/or wes# oe# = oef# and/or oes# f unctional b lock d iagram
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 7 ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 1: p in a ssignments for 62- ball lfbga (8 mm x 10 mm ) i ntel c ompatible p ackage figure 2: p in a ssignments for 63- ball tfbga and lfbga (8 mm x 10 mm ) 1236 62-tfbga p1a.1 nc nc a20 a16 wef# v sss wp# lbs# a18 nc a11 a8 ry/by# rst# nc ubs# a17 a5 a15 a10 a19 oes# a7 a4 a14 a9 dq11 a6 a0 a13 dq15 dq13 dq12 dq9 a3 bef# a12 wes# dq6 bes2 dq10 dq8 a2 v ssf v ssf dq14 dq4 v dds dq2 dq0 a1 oef# nc dq7 dq5 v ddf dq3 dq1 bes1# nc nc nc a b c d e f g h j k 8 7 6 5 4 3 2 1 top view (balls facing down) sst32hf1641x/32x1x 1236 63-tfbga p2.2 a11 a8 we# wp# lbs# a7 a15 a12 a19 bes2 rst# ubs# a6 a3 a21 a13 a9 a20 ry/by# a18 a5 a2 nc a14 a10 a17 a4 a1 a16 nc dq6 dq1 v ss a0 nc dq15 dq13 dq4 dq3 dq9 oe# bef# nc nc nc nc nc nc nc v ss dq7 dq12 v dds v ddf dq10 dq0 bes1# dq14 dq5 nc dq11 dq2 dq8 a b c d e f g h j k 8 7 6 5 4 3 2 1 top view (balls facing down)
8 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 table 3: p in d escription symbol pin name functions a ms 1 to a 0 address inputs to provide flash address, a ms -a 0 . to provide sram address, a ms -a 0 dq 15 -dq 0 data inputs/outputs to output data during read cycles and receive input data during write cycles. data is internally latched during a flash erase/program cycle. the outputs are in tri-state when oe# is high or bes1# is high or bes2 is low and bef# is high. bef# flash memory bank enable to activate the flash memory bank when bef# is low bes1# sram memory bank enable to activate the sram memory bank when bes1# is low bes2 sram memory bank enable to activate the sram memory bank when bes2 is high oef# 2 output enable to gate the data output buffers for flash 2 only oes# 2 output enable to gate the data output buffers for sram 2 only wef# 2 write enable to control the write operations for flash 2 only wes# 2 write enable to control the write operations for sram 2 only oe# output enable to gate the data output buffers we# write enable to control the write operations ubs# upper byte control (sram) to enable dq 15 -dq 8 lbs# lower byte control (sram) to enable dq 7 -dq 0 wp# write protect to protect and unprotect sectors from erase or program operation rst# reset to reset and return the device to read mode ry/by# ready/busy# to output the status of a program or erase operation ry/by# is a open drain output, so a 10k ? - 100k ? pull-up resistor is required to allow ry/by# to transition high indicating the device is ready to read. v ssf 2 ground flash 2 only v sss 2 ground sram 2 only v ss ground v dd f power supply (flash) 2.7-3.3v power supply to flash only v dd s power supply (sram) 2.7-3.3v power supply to sram only nc no connection unconnected pins t3.0 1236 1. a ms = most significant address a ms = a 19 for sst32hf1641x, a 20 for sst32hf32x1x, and a 21 for sst32hf64xx1x 2. ls and tbd? packages only
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 9 ?2003 silicon storage technology, inc. s71236-00-000 7/03 table 4: o perational m odes s election 1 mode bef# bes1# bes2 2 oe# 3 we# 3 lbs# ubs# dq 0-7 dq 8-15 full standby v ih v ih x xxxxhigh-zhigh-z xv il xxxx output disable v ih v il v ih v ih v ih x x high-z high-z v il v ih xxv ih v ih v il v ih xv ih v ih x x high-z high-z xv il flash read v il v ih xv il v ih xxd out d out xv il flash write v il v ih x v ih v il xx d in d in xv il flash erase v il v ih xv ih v il xx x x xv il sram read v ih v il v ih v il v ih v il v il d out d out v ih v il high-z d out v il v ih d out high-z sram write v ih v il v ih xv il v il v il d in d in v ih v il high-z d in v il v ih d in high-z product identification 4 v il v ih x v il v ih x x manufacturer?s id 5 device id 5 xv il t4.0 1236 1. x can be v il or v ih , but no other value. 2. do not apply bef# = v il , bes1# = v il and bes2 = v ih at the same time 3. oe# = oef# and oes# we# = wef# and wes# for ls and tbd? packages only 4. software mode only 5. with a ms -a 1 = 0;sst manufacturer?s id = 00bfh, is read with a 0 =0, sst32hf1641x device id = 234bh, is read with a 0 =1, sst32hf32x1x device id = 235bh, is read with a 0 =1, sst32hf64xx1x device id = 236bh, is read with a 0 =1.
10 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 table 5: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 5555h aah 2aaah 55h 5555h a0h wa 3 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x 4 50h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h erase-suspend xxxxh b0h erase-resume xxxxh 30h query sec id 5 5555h aah 2aaah 55h 5555h 88h user security id word-program 5555h aah 2aaah 55h 5555h a5h wa 6 data user security id program lock-out 5555h aah 2aaah 55h 5555h 85h xxh 6 0000h software id entry 7,8 5555h aah 2aaah 55h 5555h 90h software id exit 9,10 /sec id exit 5555h aah 2aaah 55h 5555h f0h software id exit 9,10 /sec id exit xxh f0h t5.0 1236 1. address format a 14 -a 0 (hex). addresses a 15 -a 19 can be v il or v ih , but no other value, for command sequence for sst32hf1641x, addresses a 15 -a 20 can be v il or v ih , but no other value, for command sequence for sst32hf32x1x, addresses a 15 - a 21 can be v il or v ih , but no other value, for command sequence for sst32hf64xx1x. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for command sequence 3. wa = program word address 4. sa x for sector-erase; uses a ms -a 11 address lines ba x , for block-erase; uses a ms -a 15 address lines a ms = most significant address a ms = a 19 for sst32hf1641x, a 20 for sst32hf32x1x, and a 21 for sst32hf64xx1x. 5. with a ms -a 4 = 0; sec id is read with a 3 -a 0 , sst id is read with a 3 = 0 (address range = 000000h to 000007h), user id is read with a 3 = 1 (address range = 000010h to 000017h). lock status is read with a 7 -a 0 = 0000ffh. unlocked: dq 3 = 1 / locked: dq 3 = 0. 6. valid word-addresses for sec id are from 000000h-000007h and 000010h-000017h. 7. the device does not remain in software product id mode if powered down. 8. with a ms -a 1 =0; sst manufacturer id = 00bfh, is read with a 0 = 0, sst32hf1641x device id = 234bh, is read with a 0 = 1, sst32hf32x1x device id = 235bh, is read with a 0 = 1, sst32hf64xx1x device id = 236bh, is read with a 0 = 1, a ms = most significant address a ms = a 19 for sst32hf1641x, a 20 for sst32hf32x1x, and a 21 for sst32hf64xx1x. 9. both software id exit operations are equivalent 10. if users never lock after programming, sec id can be programm ed over the previously unprogramm ed bits (data=1) using the sec id mode again (the programmed ?0? bits cannot be reversed to ?1?). valid word-addresses for sec id are from 000000h-000007h and 000010h-000017h.
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 11 ?2003 silicon storage technology, inc. s71236-00-000 7/03 absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v dd 1 +0.3v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd 1 +1.0v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. v dd = v ddf and v dds 2. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd commercial 0c to +70c 2.7-3.3v extended -20c to +85c 2.7-3.3v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 19 and 20
12 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 table 6: dc o perating c haracteristics (v dd = v ddf and v dds = 2.7-3.3v) symbol parameter limits test conditions min max units i dd active v dd current address input = v ilt /v iht, at f=1/t rc min, v dd =v dd max, all dqs open read oe#=v il , we#=v ih flash 18 ma bef#=v il , bes1#=v ih , or bes2=v il sram 30 ma bef#=v ih , bes1#=v il , bes2=v ih concurrent operation 40 ma bef#=v ih , bes1#=v il , bes2=v ih write 1 we#=v il flash 35 ma bef#=v il , bes1#=v ih , or bes2=v il , oe#=v ih sram 30 ma bef#=v ih , bes1#=v il , bes2=v ih i sb standby v dd current sst32hfx1 sst32hfx1c 110 30 a a v dd = v dd max, bef#=bes1#=v ihc , bes2=v ilc i rt reset v dd current 30 a reset=v ss 0.3v i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7 v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v olf flash output low voltage 0.2 v i ol =100 a, v dd =v dd min v ohf flash output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min v ols sram output low voltage 0.4 v iol =1 ma, v dd =v dd min v ohs sram output high voltage 2.2 v ioh =-500 a, v dd =v dd min t6.0 1236 1. i dd active while erase or program is in progress.
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 13 ?2003 silicon storage technology, inc. s71236-00-000 7/03 table 7: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t7.0 1236 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. table 8: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 12 pf t8.0 1236 table 9: f lash r eliability c haracteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t9.0 1236
14 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 ac characteristics table 10: sram r ead c ycle t iming p arameters symbol parameter sst32hfx1/x1c-70 sst32hfx1/x1c-90 units min max min max t rcs read cycle time 70 90 ns t aas address access time 70 90 ns t bes bank enable access time 70 90 ns t oes output enable access time 35 45 ns t byes ubs#, lbs# access time 70 90 ns t blzs 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. bes# to active output 0 0 ns t olzs 1 output enable to active output 0 0 ns t bylzs 1 ubs#, lbs# to active output 0 0 ns t bhzs 1 bes# to high-z output 25 35 ns t ohzs 1 output disable to high-z output 0 25 0 35 ns t byhzs 1 ubs#, lbs# to high-z output 35 45 ns t ohs output hold from address change 10 10 ns t10.0 1236 table 11: sram w rite c ycle t iming p arameters symbol parameter sst32hfx1/x1c-70 sst32hfx1/x1c-90 units min max min max t wcs write cycle time 70 90 ns t bws bank enable to end-of-write 60 80 ns t aws address valid to end-of-write 60 80 ns t asts address set-up time 0 0 ns t wps write pulse width 60 80 ns t wrs write recovery time 0 0 ns t byws ubs#, lbs# to end-of-write 60 80 ns t odws output disable from we# low 30 40 ns t oews output enable from we# high 0 0 ns t dss data set-up time 30 40 ns t dhs data hold from write time 0 0 ns t11.0 1236
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 15 ?2003 silicon storage technology, inc. s71236-00-000 7/03 table 12: f lash r ead c ycle t iming p arameters v dd = 2.7-3.6v symbol parameter sst32hfx1/x1c-70 sst32hfx1/x1c-90 units min max min max t rc read cycle time 70 90 ns t ce chip enable access time 70 90 ns t aa address access time 70 90 ns t oe output enable access time 35 45 ns t blz 1 bef# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t bhz 1 bef# high to high-z output 20 30 ns t ohz 1 oe# high to high-z output 20 30 ns t oh 1 output hold from address change 0 0 ns t rp 1 rst# pulse width 500 500 ns t rhr 1 rst# high before read 50 50 ns t ry 1,2 rst# pin low to read mode 20 20 s t12.0 1236 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. 2. this parameter applies to sector-e rase, block-erase and program operations. this parameter does not apply to chip-erase operations. table 13: f lash p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp word-program time 10 s t as address setup time 0 ns t ah address hold time 30 ns t bs we# and bef# setup time 0 ns t bh we# and bef# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t bp bef# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. we# pulse width high 30 ns t bph 1 bef# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t by 1 ry/by# delay time 90 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t13.1 1236
16 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 3: sram r ead c ycle t iming d iagram addresses a mss-0 dq 15-0 ubs#, lbs# oe# bes1# bes2 t rcs t aas t bes t oes t blzs t olzs t byes t bylzs t byhzs data valid t ohzs t bhzs t ohs 1236 f03.1 t bes note: a mss = most significant sram address a mss = a 17 for sst32hf1641x/3241x, a 18 for sst32hf3281x/6481x, and a 19 for sst32hf64161x
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 17 ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 4: sram w rite c ycle t iming d iagram (we# c ontrolled ) 1 note: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. if bes1# goes low or bes2 goes high coincident with or after we# goes low, the output will remain at high impedance. if bes1# goes high or bes2 goes low coincident with or be fore we# goes high, the output will remain at high impedance. because d in signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. a mss = most significant sram address a mss = a 17 for sst32hf1641x/3241x, a 18 for sst32hf3281x/6481x, and a 19 for sst32hf64161x t aws addresses a mss 3 -0 bes1# bes2 we# ubs#, lbs# t wps t wrs t wcs t asts t bws t bws t byws t odws t oews t dss t dhs 1236 f04.1 note 2 note 2 dq 15-8, dq 7-0 valid data in
18 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 5: sram w rite c ycle t iming d iagram (ubs#, lbs# c ontrolled ) 1 addresses a mss 3 -0 we# bes1# bes2 t bws t bws t aws t wcs t wps t wrs t asts t byws dq 15-8, dq 7-0 valid data in note 2 note 2 t dss t dhs ubs#, lbs# 1236 f05.1 note: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. because d in signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. a mss = most significant sram address a mss = a 17 for sst32hf1641x/3241x, a 18 for sst32hf3281x/6481x, and a 19 for sst32hf64161x
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 19 ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 6: f lash r ead c ycle t iming d iagram figure 7: f lash we# c ontrolled p rogram c ycle t iming d iagram 1236 f06.1 addresses a msf-0 dq 15-0 we# oe# bef# t be t rc t aa t oe t olz v ih high-z t blz t oh t bhz high-z data valid data valid t ohz note: a msf = most significant flash address a msf = a 19 for sst32hf1641x, a 20 for sst32hf32x1x, and a 21 for sst32hf64xx1x 1236 f07.1 address a msf-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs t by bef# ry/by# 5555 2aaa 5555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# t br t bp valid note: a msf = most significant flash address a msf = a 19 for sst32hf1641x, a 20 for sst32hf32x1x, and a 21 for sst32hf64xx1x
20 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 8: bef# c ontrolled f lash p rogram c ycle t iming d iagram figure 9: f lash d ata # p olling t iming d iagram valid 1236 f08.1 address a msf-0 dq 15-0 t dh t bph t ds t bp t ah t as t bh t bs we# 5555 2aaa 5555 addr xxaa xx55 xxa0 data word (addr/data) oe# bef# t bp t by ry/by# t br note: a msf = most significant flash address a msf = a 19 for sst32hf1641x, a 20 for sst32hf32x1x, and a 21 for sst32hf64xx1x 1236 f09.0 addresses a msf-0 dq 7 data data# data# data we# oe# bef# t oeh t oe t be t oes note: a msf = most significant flash address a msf = a 19 for sst32hf1641x, a 20 for sst32hf32x1x, and a 21 for sst32hf64xx1x
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 21 ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 10: f lash t oggle b it t iming d iagram figure 11: we# c ontrolled f lash c hip -e rase t iming d iagram 1236 f10.0 addresses a msf-0 dq 6 and dq 2 we# oe# bef# t oe t oeh t be t oes two read cycles with same outputs note: a msf = most significant flash address a msf = a 19 for sst32hf1641x, a 20 for sst32hf32x1x, and a 21 for sst32hf64xx1x valid t br 1236 f11.1 address a msf-0 dq 15-0 we# 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# bef# six-byte code for chip-erase t sce t wp t by ry/by# note: a msf = most significant flash address a msf = a 19 for sst32hf1641x, a 20 for sst32hf32x1x, and a 21 for sst32hf64xx1x this device also supports bef# controlled chip-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are meet. (see table 13.) x can be v il or v ih, but no other value.
22 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 12: we# c ontrolled f lash b lock -e rase t iming d iagram 1236 f13.1 address a msf-0 dq 15-0 we# 5555 2aaa 2aaa 5555 5555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# bef# six-byte code for block-erase t wp t by ry/by# valid t br t be note: a msf = most significant flash address a msf = a 19 for sst32hf1641x, a 20 for sst32hf32x1x, and a 21 for sst32hf64xx1x this device also supports bef# controlled block-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are meet. (see table 13.) ba x = block address
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 23 ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 13: we# c ontrolled f lash s ector -e rase t iming d iagram 1236 f12.1 address a msf-0 dq 15-0 we# 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# bef# six-byte code for sector-erase t wp t by ry/by# valid t br t se note: a msf = most significant flash address a msf = a 19 for sst32hf1641x, a 20 for sst32hf32x1x, and a 21 for sst32hf64xx1x this device also supports bef# controlled sector-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are meet. (see table 13.) sa x = sector address x can be v il or v ih, but no other value.
24 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 14: s oftware id e ntry and r ead figure 15: s oftware id e xit and r eset 1236 f14.0 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 mfg id 5555 2aaa 5555 0000 0001 oe# bef# three-word sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: x can be v il or v ih, but no other value. device id - see table 2 on page 5 1236 f15.0 address a 14-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-word sequence for software id exit and reset oe# bef# xxaa xx55 xxf0 note: x can be v il or v ih, but no other value.
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 25 ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 16: f lash s ec id e ntry 1236 f27.0 address a msf-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 oe# bef# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx88 note: a msf = most significant flash address a msf = a 19 for sst32hf1641x, a 20 for sst32hf32x1x, and a 21 for sst32hf64xx1x wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
26 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 17: rst# t iming d iagram (w hen no internal operation is in progress ) figure 18: rst# t iming d iagram (d uring p rogram or e rase operation ) 1236 f23.1 ry/by# 0v rst# bef#/oe# t rp t rhr 1236 f24.1 ry/by# bef# oe# t rp t ry t br rst#
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 27 ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 19: ac i nput /o utput r eference w aveforms figure 20: a t est l oad e xample 1236 f16.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1236 f17.0 to tester to dut c l
28 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 21: w ord -p rogram a lgorithm 1236 f18.0 start write data: xxaah address: 5555h write data: xx55h address: 2aaah write data: xxa0h address: 5555h write word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 29 ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 22: w ait o ptions 1236 f19.0 wait t bp , t sce, or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
30 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 23: s ec id/s oftware id c ommand f lowcharts x can be v il or v ih , but no other value 1236 f20.1 load data: xxaah address: 5555h software product id entry command sequence load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h sec id query entry command sequence load data: xx55h address: 2aaah load data: xx88h address: 5555h wait t ida read sec id
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 31 ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 24: s oftware id/s ec id c ommand f lowcharts 1236 f25.0 load data: xxaah address: 5555h software id exit/sec id exit command sequence load data: xx55h address: 2aaah load data: xxf0h address: 5555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation x can be v il or v ih , but no other value
32 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 25: e rase c ommand s equence 1236 f21.0 load data: xxaah address: 5555h chip-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h load data: xxaah address: 5555h wait t sce chip erased to ffffh load data: xxaah address: 5555h sector-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x load data: xxaah address: 5555h wait t se sector erased to ffffh load data: xxaah address: 5555h block-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x load data: xxaah address: 5555h wait t be block erased to ffffh note: x can be v il or v ih , but no other value.
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 33 ?2003 silicon storage technology, inc. s71236-00-000 7/03 figure 26: c oncurrent o peration f lowchart 1236 f22.0 load sdp command sequence concurrent operation flash program/erase initiated wait for end of write indication flash operation completed end concurrent operation read or write sram end wait
34 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 product ordering information device speed suffix1 suffix2 sst32 h fxxxxc -xxx -x x -x x package modifier fs = 63 ball positions s = 62 ball positions package type b = tfbga (8mm x 10mm x 1.2mm, 0.40mm ball size) l = lfbga (8mm x 10mm x 1.4mm, 0.40mm ball size) temperature range c = commercial = 0c to +70c e = extended = -20c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns 90 = 90 ns device blank = pseudosram c = standard sram hardware block protection 1 = bottom boot block sram density 1 4 = 4 mbit 8 = 8 mbit 16 = 16 mbit flash density 16 = 16 mbit 32 = 32 mbit 64 = 64 mbit voltag e h = 2.7-3.3v device family 32 = mpf + sram combomemory 1. no sram and 2 mbit sram options not currently planned. however, if business conditions merit, these devices could go into production. contact your sst sales representative for availability.
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 35 ?2003 silicon storage technology, inc. s71236-00-000 7/03 valid combinations for sst32hf1641 sst32hf1641-70-4c-bfs sst32hf1641-70-4c-ls sst32hf1641-70-4c-lfs sst32hf1641-90-4c-bfs sst32hf1641-90-4c-ls sst32hf1641-90-4c-lfs sst32hf1641-70-4e-bfs sst32hf1641-70-4e-ls sst32hf1641-70-4e-lfs sst32hf1641-90-4e-bfs sst32hf1641-90-4e-ls sst32hf1641-90-4e-lfs valid combinations for sst32hf1641c sst32hf1641c-70-4c-bfs sst32hf1641c-70-4c-ls sst32hf1641c-70-4c-lfs sst32hf1641c-90-4c-bfs sst32hf1641c-90-4c-ls sst32hf1641c-90-4c-lfs sst32hf1641c-70-4e-bfs sst32hf1641c-70-4e-ls sst32hf1641c-70-4e-lfs SST32HF1641C-90-4E-BFS sst32hf1641c-90-4e-ls sst32hf1641c-90-4e-lfs valid combinations for sst32hf3241 sst32hf3241-70-4c-bfs sst32hf3241-70-4c-ls sst32hf3241-70-4c-lfs sst32hf3241-90-4c-bfs sst32hf3241-90-4c-ls sst32hf3241-90-4c-lfs sst32hf3241-70-4e-bfs sst32hf3241-70-4e-ls sst32hf3241-70-4e-lfs sst32hf3241-90-4e-bfs sst32hf3241-90-4e-ls sst32hf3241-90-4e-lfs valid combinations for sst32hf3241c sst32hf3241c-70-4c-bfs sst32hf3241c-70-4c-ls sst32hf3241c-70-4c-lfs sst32hf3241c-90-4c-bfs sst32hf3241c-90-4c-ls sst32hf3241c-90-4c-lfs sst32hf3241c-70-4e-bfs sst32hf3241c-70-4e-ls sst32hf3241c-70-4e-lfs sst32hf3241c-90-4e-bfs sst32hf3241c-90-4e-ls sst32hf3241c-90-4e-lfs valid combinations for sst32hf3281 sst32hf3281-70-4c-bfs sst32hf3281-70-4c-ls sst32hf3281-70-4c-lfs sst32hf3281-90-4c-bfs sst32hf3281-90-4c-ls sst32hf3281-90-4c-lfs sst32hf3281-70-4e-bfs sst32hf3281-70-4e-ls sst32hf3281-70-4e-lfs sst32hf3281-90-4e-bfs sst32hf3281-90-4e-ls sst32hf3281-90-4e-lfs valid combinations for sst32hf3281c sst32hf3281c-70-4c-bfs sst32hf3281c-70-4c-ls sst32hf3281c-70-4c-lfs sst32hf3281c-90-4c-bfs sst32hf3281c-90-4c-ls sst32hf3281c-90-4c-lfs sst32hf3281c-70-4e-bfs sst32hf3281c-70-4e-ls sst32hf3281c-70-4e-lfs sst32hf3281c-90-4e-bfs sst32hf3281c-90-4e-ls sst32hf3281c-90-4e-lfs valid combinations for sst32hf6481 sst32hf6481-70-4c-bfs sst32hf6481-70-4c-tbd ? sst32hf6481-70-4c-lfs sst32hf6481-90-4c-bfs sst32hf6481-90-4c-tbd ? sst32hf6481-90-4c-lfs sst32hf6481-70-4e-bfs sst32hf6481-70-4e-tbd ? sst32hf6481-70-4e-lfs sst32hf6481-90-4e-bfs sst32hf6481-90-4e-tbd ? sst32hf6481-90-4e-lfs valid combinations for sst32hf6481c sst32hf6481c-70-4c-bfs sst32hf6481c-70-4c-tbd ? sst32hf6481c-70-4c-lfs sst32hf6481c-90-4c-bfs sst32hf6481c-90-4c-tbd ? sst32hf6481c-90-4c-lfs sst32hf6481c-70-4e-bfs sst32hf6481c-70-4e-tbd ? sst32hf6481c-70-4e-lfs sst32hf6481c-90-4e-bfs sst32hf6481c-90-4e-tbd ? sst32hf6481c-90-4e-lfs
36 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 valid combinations for sst32hf64161 sst32hf64161-70-4c-bfs sst32hf64161-70-4c-tbd ? sst32hf64161-70-4c-lfs sst32hf64161-90-4c-bfs sst32hf64161-90-4c-tbd ? sst32hf64161-90-4c-lfs sst32hf64161-70-4e-bfs sst32hf64161-70-4e-tbd ? sst32hf64161-70-4e-lfs sst32hf64161-90-4e-bfs sst32hf64161-90-4e-tbd ? sst32hf64161-90-4e-lfs valid combinations for sst32hf64161c sst32hf64161c-70-4c-bfs sst32hf64161c-70-4c-tbd ? sst32hf64161c-70-4c-lfs sst32hf64161c-90-4c-bfs sst32hf64161c-90-4c-tbd ? sst32hf64161c-90-4c-lfs sst32hf64161c-70-4e-bfs sst32hf64161c-70-4e-tbd ? sst32hf64161c-70-4e-lfs sst32hf64161c-90-4e-bfs sst32hf64161c-90-4e-tbd ? sst32hf64161c-90-4e-lfs note: valid combinations are those products in mass production or will be in mass production. a bga package with a height of 1.2mm is not currently planned. however, if business conditions merit, these devices could go into production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations. ?: denotes a bga package with 64 balls and a height of 1.4mm currently under development.
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 37 ?2003 silicon storage technology, inc. s71236-00-000 7/03 packaging diagrams 63- ball t hin - profile , f ine - pitch b all g rid a rray (tfbga) 8 mm x 10 mm sst p ackage c ode : bfs a1 corner k j h g f e d c b a a b c d e f g h j k bottom view top view 8 7 6 5 4 3 2 1 8.0 0.1 0.40 0.05 (63x) a1 corner 10.0 0.1 0.80 5.60 0.80 7.20 63-tfbga-bfs-8x10-400mic-0 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registered. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 8 7 6 5 4 3 2 1 1mm side view seating plane 0.32 0.05 1.2 max 0.12
38 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c ?2003 silicon storage technology, inc. s71236-00-000 7/03 62- ball l ow - profile , f ine - pitch b all g rid a rray (lfbga) 8 mm x 10 mm sst p ackage c ode : ls a1 corner k j h g f e d c b a a b c d e f g h j k bottom view top view 8 7 6 5 4 3 2 1 8.00 0.20 0.40 0.05 (62x) a1 corner 10.00 0.20 0.80 5.60 0.80 7.20 62-lfbga-ls-8x10-400mic-3 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registered. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. the actual shape of the corners may be slightly different than as portrayed in the drawing. 8 7 6 5 4 3 2 1 1mm side view seating plane 0.32 0.05 1.30 0.10 0.12
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf1641 / sst32hf3241 / sst32hf3281 / sst32hf6481 / sst32hf64161 sst32hf1641c / sst32hf3241c / sst32hf3281c / sst32hf6481c / sst32hf64161c 39 ?2003 silicon storage technology, inc. s71236-00-000 7/03 63- ball l ow - profile , f ine - pitch b all g rid a rray (lfbga) 8 mm x 10 mm sst p ackage c ode : lfs table 14: r evision h istory number description date 00 initial release jul 2003 a1 corner k j h g f e d c b a a b c d e f g h j k bottom view top view 8 7 6 5 4 3 2 1 8.0 0.1 0.40 0.05 (63x) a1 corner 10.0 0.1 0.80 5.60 0.80 7.20 63-lfbga-lfs-8x10-400mic-0 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registered. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size: 0.32 mm 8 7 6 5 4 3 2 1 1mm side view seating plane 0.32 0.05 1.3 0.1 0.12 silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

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